Yosys Open SYnthesis Suite, including Verilog synthesizer
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Release | Stable | Testing |
---|---|---|
Fedora Rawhide | 0.12-2.20211209gitcdb5711.fc36 | - |
Fedora 35 | 0.9-16.20210904git50be8fd.fc35 | - |
Fedora 34 | 0.9-11.20210310git26e01a6.fc34 | - |
You can contact the maintainers of this package via email at
yosys dash maintainers at fedoraproject dot org
.