Parse Verilog $readmemh or $readmemb text file
The Verilog Hardware Description Language (HDL) provides a convenient way to load a memory during logic simulation. The $readmemh() and $readmemb() system tasks are used in the HDL source code to import the contents of a text file into a memory variable.
Release | Stable | Testing |
---|---|---|
Fedora Rawhide | 0.05-18.fc35 | - |
Fedora 35 | 0.05-18.fc35 | - |
Fedora 34 | 0.05-16.fc34 | - |
You can contact the maintainers of this package via email at
perl-Verilog-Readmem dash maintainers at fedoraproject dot org
.